1. Field of the Invention
The present invention relates to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor devices having thin film transistors (TFTs) and methods of fabricating the same.
2. Description of Related Art
In general, semiconductor integrated circuits (ICs) widely employ discrete devices such as MOS transistors as switching devices. Most of the MOS transistors are directly formed on a semiconductor substrate. That is, the MOS transistors include channel regions and source and drain regions, which are formed in the semiconductor substrate. In this case, the MOS transistors may be referred to as bulk MOS transistors.
When the semiconductor ICs employ the bulk MOS transistors, increasing the integration density of the semiconductor ICs is reaching a technical limit. In particular, if the semiconductor ICs employ complementary metal-oxide-semiconductor (CMOS) circuits, it is more difficult to improve the integration density thereof. This is because a latch-up phenomenon occurs in the CMOS circuits. In recent years, thin film transistors (TFTs), which are stacked on the semiconductor substrate, are widely used to increase the integration density of the semiconductor ICs and also overcome the latch-up phenomenon.
FIG. 1A is a plan view of a conventional semiconductor device having a TFT, FIG. 1B is a cross-sectional view taken along line I-I′ of FIG. 1A, and FIG. 1C is a cross-sectional view taken along line II-II′ of FIG. 1A.
Referring to FIGS. 1A, 1B and 1C, an isolation layer 10 is provided in a predetermined region of a semiconductor substrate 5 to define an active region 10a. A pair of first impurity regions, i.e., a first drain region 20d and a first source region 20s, are disposed in the active region 10a and spaced apart from each other. A bulk gate electrode 15 is disposed to cross over a channel region that is disposed between the first drain region 20d and the first source region 20s. The bulk gate electrode 15 is electrically insulated from the channel region by a bulk gate insulating layer 12. Sidewalls of the bulk gate electrode 15 may be covered with a bulk gate spacer 17. The bulk gate electrode 15, the first drain region 20d, and the first source region 20s constitute a bulk MOS transistor.
A first interlayer insulating layer 22 is provided on the semiconductor substrate 5 having the bulk MOS transistor. A trench 27t is disposed in the first interlayer insulating layer 22. The trench 27t may overlap the active region 10a. A lower semiconductor body 30 is filled in the trench 27t. A pair of second impurity regions, i.e., a lower drain region 30d and a lower source region 30s, are disposed in the lower semiconductor body 30 and spaced apart from each other. A lower gate electrode 35 is disposed to cross over a channel region that is disposed between the lower drain region 30d and the lower source region 30s. The lower gate electrode 35 is electrically insulated from the channel region by a lower gate insulating layer 32. Sidewalls of the lower gate electrode 35 may be covered with a lower gate spacer 37. The lower gate electrode 35, the lower drain region 30d, and the lower source region 30s constitute a lower TFT. Also, as can be seen from FIG. 1A, the lower TFT may overlap the bulk MOS transistor. That is, the lower semiconductor body 30 may overlap the active region 10a, and the lower gate electrode 35 may overlap the bulk gate electrode 15.
Furthermore, the first drain region 20d may be exposed by a lower node contact hole 25h that is formed through the first interlayer insulating layer 22, and the lower node contact hole 25h may be filled with a lower semiconductor node plug 25. The lower semiconductor node plug 25 may be in contact with a bottom surface of the lower semiconductor body 30. For example, the lower semiconductor node plug 25 may be in contact with the lower drain region 30d. The lower semiconductor node plug 25 may be a semiconductor plug that is formed by a selective epitaxial growth (SEG) process using the first drain region 20d as a seed layer. Accordingly, when the semiconductor substrate 5 is a single crystalline semiconductor substrate, the lower semiconductor node plug 25 may also have a single crystalline structure.
Also, the lower semiconductor body 30 may be epitaxially grown using the lower semiconductor node plug 25 as a seed layer. Accordingly, when the lower semiconductor node plug 25 is a single crystalline semiconductor plug, the lower semiconductor body 30 may also have a single crystalline structure.
A second interlayer insulating layer 40 is provided on the semiconductor substrate 5 having the lower TFT. When the lower semiconductor node plug 25 has the same conductivity type as the first drain region 20d, at least the lower drain region 30 may be exposed by a metal node contact hole 42h that is formed through the first and second interlayer insulating layers 22 and 40, and the metal node contact hole 42h may be filled with a metal node plug 42. As a result, the metal node plug 42 is in contact with at least the lower drain region 30d. When the lower semiconductor node plug 25 has a different conductivity type from the first drain region 20d, the metal node plug 42 may extend and come into contact with the first drain region 20d. Further, the metal node plug 42 may be in contact with not only the drain regions 30d and 20d but also the lower semiconductor node plug 25.
A third interlayer insulating layer 45 is provided on the semiconductor substrate 5 having the second interlayer insulating layer 40 and the metal node plug 42. The metal node plug 42 may be exposed by a first lower interconnection contact hole 46a that is formed through the third interlayer insulating layer 45, and the lower source region 30s may be exposed by a second lower interconnection contact hole 46b that is formed through the second and third interlayer insulating layers 40 and 45. Also, the first source region 20s may be exposed by a third lower interconnection contact hole 46c that is formed through the first through third interlayer insulating layers 22, 40, and 45, and the lower gate electrode 35 may be exposed by a fourth lower interconnection contact hole 46d that is formed through the second and third interlayer insulating layers 40 and 45. Further, the bulk gate electrode 15 may be exposed by a fifth lower interconnection contact hole 46e that is formed through the first through third interlayer insulating layers 22, 40, and 45. The first through fifth lower interconnection contact holes 46a, 46b, 46c, 46d, and 46e may be filled with first through fifth lower interconnection contact plugs 47a, 47b, 47c, 47d, and 47e, respectively.
As can be seen from FIGS. 1B and 1C, when the semiconductor device includes a multi-layered transistor, the contact plugs 47a, 47b, 47c, 47d, and 47e are provided to apply a voltage to the bulk MOS transistor and the lower TFT. In this case, since the lower TFT is disposed over the bulk MOS transistor, the third and fifth lower interconnection contact plugs 47c and 47e and the bulk gate electrode 15, which are used to apply a voltage to the bulk MOS transistor, are disposed close to lateral and bottom surfaces of the lower TFT. Accordingly, as the body energy potential of the lower semiconductor body 30 varies with surrounding voltage conditions, the characteristics of the lower TFT may change. That is, the characteristics of the lower TFT depend on gate, source, and drain voltages of the lower TFT, like a bulk transistor or a silicon on insulator (SOI) transistor, and also are affected by circumstances (e.g., energy potential) around the lower TFT. For example, even if a voltage of 0 V is applied to the lower gate electrode 35 to turn off the lower TFT, once a voltage Vcc is applied to the bulk gate electrode 15 through the fifth lower interconnection contact plug 47e, an upper region of the lower semiconductor body 30 of the lower TFT remains turned off under the influence of the lower gate electrode 35, whereas lower and lateral regions of the lower semiconductor body 30 are more affected by the bulk gate electrode 15 and contact voltages as can be seen from reference characters ‘A1’ and ‘B1’, respectively, thus greatly increasing an off current of the lower TFT.
Therefore, it is necessary to develop semiconductor devices having TFTs in which a lower semiconductor body is not significantly affected by the surrounding energy potential.